CH563

Overview

CH563 is a CPU with 32-bit reduced instruction sets. The system clock frequency is 100MHz by default, and can be up to 130MHz. The CH563 integrates high-speed USB interface and 10/100M network interface that support DMA (built-in PHY). CH563 can be widely used in various embedded applications, with features of highly integrated peripherals and high performance.

System Block Diagram

Features

• 32-bit RISC reduced instruction sets, 100MHz system clock frequency.
• 224KB CodeFlash, 28KB DATA Flash, 64KB SRAM.
• USB2.0 high-speed master/slave interface (built-in PHY).
• 10/100M network interface (built-in PHY).
• 4 x 28-bit timers.
• Single passive parallel and intel timing bus interface.
• 3-channel 10-bit ADC.
• 2 SPIs, 2 UARTs.
• 74 GPIOs.
• Low-power Sleep mode.
• Packages: LQFP64M, LQFP128.