CH554

Overview

CH554 is an enhanced E8051 core MCU, compatible with MCS51 instruction set. 79% of its instructions are single-byte single-cycle instructions. CH554 has a built-in 24MHz clock source, built-in 1K+256B RAM and 16KB iFlash-ROM. CH554 provides abundant interface sources, including ADC, 3 timers and signal capture and PWM, 2 UARTs, SPI, etc. CH554 provides 6-channel capacitive detection module, and it supports up to 15 touch-keys in mutual capacitance mode. CH554 has built-in full-speed USB controller, and supports USB Host mode and USB Device mode.

System Block Diagram

Features

• Enhanced E8051 core CPU, the speed is 8-15 times faster than that of standard MCS51, with special XRAM data fast copy instruction.
• Built-in 14KB Code Flash and 2KB BootLoader. ISP through USB or UART.
• Built-in 1KB XRAM and internal 256B iRAM. 128-byte DataFlash. Support read/write by bytes.
• Built-in 6-channel capacitive detection module. CH554 supports up to 15 touch-keys, and supports independent timing interrupt.
• Built-in USB controller and USB transceiver, support USB2.0 full-speed and low-speed host/device mode. CH554 supports up to 64 bytes of data packet with built-in FIFO. DMA capability.
• Support USB Type-C master/slave detect, control and configure power supply, to implement Type-C power management function.
• 3 timers/counters. 2-channel signal capture and 2-channel PWM output.
• 2 full-duplex UARTs support high-baud-rate communication. UART0 is a standard MCS51 serial port.
• One SPI communication interface with built-in FIFO supports master/slave mode.
• 4-channel 8-bit ADC. Voltage comparator.
• Built-in 24MHz clock source and PLL. An external crystal oscillator is also supported.
• Packages: TSSOP20, MSOP10, QFN16 and SOP16.